A phase-change memory as one of programmable memories with a resistor is a nonvolatile memory which makes use of the behavior that applying heat to a material of chalcogenide series (Ge, Sb, Te) produces transition between an amorphous phase (high resistance) and a crystalline phase (low resistance). Although the phase change generally occurs due to Joule's heat generated by electric current and energization time between the high resistance state (Reset) and the low resistance state (Set), the writing speed of the phase-change memory is faster than that of the flash memory. The phase-change memory has been developed in view of substitution for DRAM or SRAM as an application of the phase-change memory.
The phase-change memory is designed by arranging memory cells having phase-change elements in a matrix form and by laying-out bit lines and word lines at right angles each other so that a desired memory cell can be accessed (See, for example, Patent Document 1 and Patent Document 2).
In the phase-change memory, as the memory cells become finer and finer, the driving current performance of the memory cell transistor decreases, resulting in instable data writing. As a means to increase the driving current of the transistor, the effective channel width W is widened. For example, Patent Document 3 discloses a nonvolatile semiconductor memory device in which two field-effect transistors are disposed along both sides of a memory cell contact as switching transistors of a switching element.
FIGS. 7A and 7B show a layout to explain a structure of the phase-change memory disclosed in Patent Document 3. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along a P-Q line of FIG. 7A. In FIGS. 7A and 7B, the phase-change memory cell comprises a memory cell contact 95 having a contact layer 110, a chalcogenide layer 100 and a heater layer 105 and switching transistors 116, 118. The memory cell contact 95 electrically connects a drain region 120 shared in common by the switching transistors 116, 118 to a bit line BL. The switching transistor 116 uses a word line CWL as a gate and shares a source region 125 with an adjacent transistor. The switching transistor 118 uses a word line WWL as a gate and shares the source region 125 with the adjacent transistor. The switching transistors 116, 118 are arranged in a row along both the sides of the memory cell contact 95 and turn on at writing time to pass data writing current. A gate width twice as wide as the dimension of the memory cell can be secured in the entire switching transistor, a driving current performance enough for the data writing can be obtained even though the memory cells are made smaller.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2004-110867A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2005-150243A
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2005-071500A